Computer graphics display systems, e.g., CAD/CAM graphics workstations, are widely used to generate and display two-dimensional images of three-dimensional objects for scientific, engineering, manufacturing and other applications. In such high performance computer graphics systems, digital representations of computer generated images conventionally reside in an array of video RAM, which collectively embody the system frame buffer. The rate at which the frame buffer can be updated/read is a critical parameter in the performance of the entire graphics system. One presently preferred graphics display consists of an array of 1280.times.1024 screen pixels. With such a display monitor, the common practice in industry is to employ five separate video RAMS in the frame buffer for storing variable information corresponding to each pixel of the screen.
By way of a common example, each of the five video RAMs may comprise a 512.times.512, eight bit deep RAM memory. Pixel locations are addressed in the raster engine as X,Y coordinate pairs which must be converted into a corresponding address to one of these five video RAMs of the associated frame buffer. The 1280.times.1024 pixel array of the display monitor is typically subdivided into a plurality of groupings or tiles each of which may, for example, be as basic as a sequence of five pixels in a row. Between each five pixel grouping, column address boundaries are defined. Assuming that there are five pixels in each row grouping of pixels, then the converted Y address for a given X,Y pixel location will be defined as X/5. Similarly, because each video RAM comprises a 512.times.512 array, two rows of screen pixels may be scanned simultaneously. Therefore, the particular row location is defined by Y/2. Finally, the video RAM module (i.e., module 0, 1, 2, 3 or 4) is identified as the remainder portion of the X address divide by five operation definitive of the column address crossing.
Division of a binary number by a binary power (1, 2, 4, 8, 16, 32, etc.) is easily obtained simply by an appropriate shift of the binary number of one bit (divide by two), two bits (divide by 4), three bits (divide by 8), etc. in the direction of less significance. However, division by five, or division by any integer number of a non-binary power, is significantly more complicated and time consuming.
An early attempt at a divide by five operation might have been implemented in software, requiring a significant amount of computing time to complete. Subsequent implementations have typically embodied one of three hardware approaches. A first technique is to use a register coupled with appropriate logic to process the X address in a number of iterations. The approach essentially comprises longhand division implemented in hardware and can be time consuming, typically requiring five clock cycles or more to complete a calculation. A second hardware approach is to implement the divide by five operation in combinatorial logic. For example, multiple levels of appropriately configured NAND gates can be used. However, this technique remains slow in terms of the delay involved to attain the necessary conversion. For example, a fifty nanosecond (50 ns) delay might be experienced in a typical system, which can be significant since today's fast processing systems are clocking at twenty nanoseconds with a fifty MHz clock. The third approach is a hybrid of the second technique wherein the combinatorial logic is pipelined with the addition of appropriate registers so that after a certain period of original latency, a non-binary power divide operation can be accomplished with every clock cycle. The problem with this approach, however, is the original latency period which obviously adds delay to the address conversion operation, as well as any associated tasks dependent thereon.
Thus, a genuine need exists in the computer processing field for a novel hardware approach to dividing a binary number by an integer number of a non-binary power, particularly for improved access time between a raster engine and its associated frame buffer in connection with the updating/reading of pixel variable information within a graphics display system.